On the Design of Self-Testing Checkers for Modified Berger Codes

One of several approaches fo r designing highly-reliable systems relies on using error detecting codes (EDCs) and implementing digital circuits as selj-checking. One class of EDCs that has been very often used to implement selfchecking circuits are Berger codes. Although several selftesting checkers (STCs) for Berger codes have been proposed in the past, they mostly present area and delay results based on gate counts and gate levels and not on real implementations. In this work we consider real implementations and present and evaluate the area, delay and power characteristics of STCs for mod$ied Berger codes that are based on: (a) parallel counters and (bj sorting networks. Preliminary results indicate that STCs based on parallel counters are smaller and consume less power than the STCs based on sorting networks. Dept. of Computer Eng. & Informatics 26500 Patras, Greece {bakalis,kabousia} @cti.gr implement SC circuits are Berger codes, which are the optimal systematic unordered codes capable of detecting unidirectional errors of any multiplicity. The reliable operation of a checker could be ensured by implementing it as a selftesting checker (STC) which is capable of detecting its own internal faults during normal functioning. Although several STCs for Berger and equivalent codes have been proposed in the past [2]-[10], they mostly present area and delay results based on gate counts and gate levels and not on real implementations. Actually, the only work that addressed the design of low-power consumption in SC circuits deals with 2-rail STCs only [ 1 I]. In this work we consider real implementations and present and evaluate the area, delay and power characteristics of STCs for modified Berger codes that are based on: (a) parallel counters and (b) sorting networks.